sketching ir
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@ -31,11 +31,6 @@ impl fmt::Display for IrBlock {
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pub enum Instruction {
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/// Load a literal value into the `dst` register
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LoadLiteral { dst: RegId, lit: Literal },
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/// Append a list in `src` to the list in `dst`, modifying `dst`. Used for list spread
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AppendList { dst: RegId, src: RegId },
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/// Append a string in `src` to the string in `dst`, modifying `dst`. Used for string
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/// interpolation
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AppendString { dst: RegId, src: RegId },
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/// Copy a register (must be a collected value)
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Clone { dst: RegId, src: RegId },
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/// Collect a stream in a register to a value
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@ -44,20 +39,23 @@ pub enum Instruction {
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PushPositional { src: RegId },
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/// Add a list of args to the next call (spread/rest)
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AppendRest { src: RegId },
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/// Add a named arg to the next call. The `src` is optional, can be `None` if there is no value.
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PushNamed { name: Box<str>, src: Option<RegId> },
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/// Add a named arg to the next call. The `src` is optional. Register id `0` is reserved for
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/// no-value.
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PushNamed { name: Box<str>, src: RegId },
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/// Clear the argument stack for the next call
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ClearArgs,
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/// Make a call. The input is taken from `src_dst`, and the output is placed in `src_dst`,
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/// overwriting it. The argument stack is used implicitly and cleared when the call ends.
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Call { decl_id: DeclId, src_dst: RegId },
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/// Do a binary operation on `lhs` (left) and `rhs` (right) and write the result to `dst`.
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/// Do a binary operation on `lhs_dst` (left) and `rhs` (right) and write the result to
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/// `lhs_dst`.
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BinaryOp {
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dst: RegId,
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lhs_dst: RegId,
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op: Operator,
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lhs: RegId,
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rhs: RegId,
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},
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/// Follow a cell path on the `path`
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FollowCellPath { src_dst: RegId, path: RegId },
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/// Jump to an offset in this block
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Jump { index: usize },
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/// Branch to an offset in this block if the value of the `cond` register is a true boolean,
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@ -73,12 +71,6 @@ impl fmt::Display for Instruction {
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Instruction::LoadLiteral { dst, lit } => {
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write!(f, "{:15} %{}, {:?}", "load-literal", dst.0, lit)
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}
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Instruction::AppendList { dst, src } => {
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write!(f, "{:15} %{}, %{}", "append-list", dst.0, src.0)
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}
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Instruction::AppendString { dst, src } => {
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write!(f, "{:15} %{}, %{}", "append-string", dst.0, src.0)
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}
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Instruction::Clone { dst, src } => {
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write!(f, "{:15} %{}, %{}", "clone", dst.0, src.0)
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}
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@ -92,11 +84,7 @@ impl fmt::Display for Instruction {
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write!(f, "{:15} %{}", "append-rest", src.0)
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}
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Instruction::PushNamed { name, src } => {
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if let Some(src) = src {
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write!(f, "{:15} {:?}, %{}", "push-named", name, src.0)
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} else {
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write!(f, "{:15} {:?}", "push-named", name)
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}
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}
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Instruction::ClearArgs => {
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write!(f, "{:15}", "clear-args")
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@ -104,12 +92,11 @@ impl fmt::Display for Instruction {
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Instruction::Call { decl_id, src_dst } => {
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write!(f, "{:15} decl {}, %{}", "call", decl_id, src_dst.0)
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}
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Instruction::BinaryOp { dst, lhs, op, rhs } => {
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write!(
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f,
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"{:15} %{}, {:?}, %{}, %{}",
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"binary-op", dst.0, op, lhs.0, rhs.0
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)
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Instruction::BinaryOp { lhs_dst, op, rhs } => {
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write!(f, "{:15} %{}, {:?}, %{}", "binary-op", lhs_dst.0, op, rhs.0)
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}
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Instruction::FollowCellPath { src_dst, path } => {
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write!(f, "{:15} %{}, %{}", "follow-cell-path", src_dst.0, path.0)
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}
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Instruction::Jump { index } => {
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write!(f, "{:15} {}", "jump", index)
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@ -155,40 +142,39 @@ fn dummy_test() {
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let ir_block = IrBlock {
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instructions: vec![
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Instruction::LoadLiteral {
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dst: RegId(0),
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dst: RegId(1),
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lit: Literal::String("foo".into()),
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},
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Instruction::PushPositional { src: RegId(0) },
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Instruction::PushPositional { src: RegId(1) },
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Instruction::LoadLiteral {
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dst: RegId(2),
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dst: RegId(1),
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lit: Literal::Int(40),
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},
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Instruction::LoadLiteral {
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dst: RegId(3),
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dst: RegId(2),
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lit: Literal::Int(25),
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},
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Instruction::BinaryOp {
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dst: RegId(1),
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lhs_dst: RegId(1),
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op: Operator::Math(Math::Plus),
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lhs: RegId(2),
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rhs: RegId(3),
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rhs: RegId(2),
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},
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Instruction::PushNamed {
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name: "bar-level".into(),
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src: Some(RegId(1)),
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src: RegId(1),
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},
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Instruction::LoadLiteral {
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dst: RegId(4),
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dst: RegId(1),
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lit: Literal::Nothing,
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},
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Instruction::Call {
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decl_id: 40,
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src_dst: RegId(4),
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src_dst: RegId(1),
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},
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Instruction::Return { src: RegId(4) },
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Instruction::Return { src: RegId(1) },
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],
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spans: vec![],
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register_count: 5,
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register_count: 2,
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};
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println!("{}", ir_block);
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todo!();
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